Thread: Building a Desktop

Originally Posted by sycld

perhaps that's true, but tunneling and heat dissipation are different in that they are physical limits that will literally not allow the device to operate, economically or not.

as for quantum computing, it unfortunately is only more efficient than a classical computer for a rather circumscribed set of a problems, if it can be implemented at all.

All that's currently possible with quantum computing, as far as I'm aware is double digit addition.

Tunnel and Heat dissipation of course are the more pertinent issues. More so tunneling given Moores. We are at the micrometer range already, if I recall.

Originally Posted by TheOriginalGrumpySpy

All that's currently possible with quantum computing, as far as I'm aware is double digit addition.

Tunnel and Heat dissipation of course are the more pertinent issues. More so tunneling given Moores. We are at the micrometer range already, if I recall.

The things I said about QC were theoretical but rigorously-derived conclusions. Of course, you're right in that actual implementations of QC have been so small scale that all that has been done is adding two numbers together.

Also, we were in the micron range for transistors decades ago; that's why it's called "micortechnology," after all. We're around the 60 nm node now.

EDIT: I double-checked this, and it looks like the state-of-the-art that is currently in the consumer market is 45 nm transistors. 65 nm was state-of-the-art all the way back in 2007. Technology is shrinking quickly...

Also, I should clarify by saying that the size node refers to the half-pitch of the transistor array. That is, the center-to-center spacing of the transistors is twice the node size. The transistor width is around half the center-to-center spacing.